SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.

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A data path is designn implemented in a bit sliced fashion. Setup time is a requirement that the data has to be stable before the clock edge and hold time is a requirement that the data has to be stable after the clock edge.

What is known as IDDQ testing?


Eliminate logic switching that is not necessary for computation. Low Input Impedance Low delay Sensitivity to load. Iterative logic array testing What is enhancement mode FET? FPGAs can be used to implement a logic circuit with more than 20, gates whereas a CPLD can implement circuits of upto about 20, equivalent gates. A fundamental difficulty with dynamic circuits is a loss of noise immunity and a serious timing restriction on the inputs of the gate.

What is ,arks skew?

Regular event control 2. What are the various silicon wafer preparations? What are the types of ASICs? What are the applications of chip level test techniques?

What is meant by observability? What is the structural gate-level modeling? Some of the important CAD tools are: Why low power has become an important issue in the VLSI circuit realization? This multiplier is suitable for positive operands.


Channeled gate array Channel less gate array Only the interconnect is customized Only the top few mask layers are customized The interconnect uses predefined No predefined areas are set aside for spaces between rows of base cells routing between cells. The standard cell blsi also called flexible blocks in a CHIC are built of rows of standard cells.

First, the node to be faulted is selected.

Read operation is destructive. Give the different types of ASIC. If and when a discrepancy is detected between the faulted circuit response and the good circuit response, the fault is said to be detected and the simulation is stopped.

Power is the rate at which energy is delivered or exchanged; power dissipation is the rate at which energy is taken from the source VDD and converted into heat electrical energy is converted into heat energy during operation. State different types of oxidation. Delay-based timing control 2. A sequencing element with static storage employs some sort of feedback to retain its output value indefinitely.

Level-sensitive timing control 49 Give the different arithmetic operators? Give the various color coding used in stick diagram? Give the advantages of IC? What is pull down device? What is known as boundary scan register?

EC – VLSI Design 2Marks with Answer and 16Marks Question

It uses a cascade of pass transistors to implement the carry chain. Help Center Find new research papers in: Booth algorithm is a method that will vlsii the number of multiplicand multiples. It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design.


Silicon on insulator process 4. The amount of time before the clock edge that data input D must be stable the rising clock edge arrives. Short-Circuit and Open-Circuit Faults What is an antifuse? One else statement Syntax: What is stick diagram? Difference between latches and Flip Flop.

The amount of time needed for a change in a logic input to result in an initial change at an output, that is the combinational logic is guaranteed not to show any output change in response to an input change before fed time units have passed. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.

One additional capacitor is explicitly fabricated for storage purpose. Fault model is a model for how faults occur and their impact on circuits. What is known as percentage-fault coverage? Give the different types of CMOS process? This makes MOS dynamic circuits faster. State the advantages of CMOS process.

What are the different layers in MOS transistors? What are the uses of stick diagram?